A FinFET is configured by including: a projecting semiconductor layer (fin) which is formed on a surface portion of a semiconductor substrate and which has a long side direction and a short side direction; and gate electrodes formed on both side surfaces of the semiconductor layer in the short side direction via a gate insulating film. The semiconductor layer of the portion sandwiched by the gate electrodes serves as a channel region. Further, in the semiconductor layer, both sides of the channel region serve as the source and drain regions.
The FinFET can be roughly classified into a type using a bulk substrate, and a type using an SOI (Silicon On Insulator) substrate. The FinFET using the bulk substrate has an advantage that the manufacturing cost is low as compared with the type using the SOI substrate, and also has an advantage that there is no deterioration in transistor performance due to the body floating effect and the self-heating effect. On the other hand, in the FinFET using the bulk substrate, there is a problem that in the lower portion of the fin which portion is not sandwiched by the gate electrodes and which portion is hence a region hardly controlled by the gate electrode, the punch through is actually caused so as to thereby increase the off-leak current (to lower the capability of suppressing the short channel effect).
As a method for avoiding this problem, there is known a method in which a high concentration impurity layer (punch-through stopper) is formed in the lower portion of the fin (see, for example, Japanese Patent Laid-Open No. 2007-258485). However, there is a problem that the mobility of the channel region is lowered by the mixing of the impurity into the channel region at the time of formation of the punch-through stopper and by the diffusion of the punch-through stopper impurity into the channel region due to thermal diffusion.